Solid-state memories, i.e., memories formed from arrays of memory cells disposed on integrated circuits, or chips, are utilized in a wide variety of applications to store data in computers and other electronic devices. One type of solid-state memory, for example, is static random access memory (SRAM), which due to its fast access time is often used in high performance applications such as cache memories coupled to computer processors. Often, SRAM memory arrays are embedded--that is, integrated with a computer processor and/or other logic on a single chip.
Due to processing variations during the manufacture of chips incorporating SRAM's or other solid-state memories, memory testing is often required during manufacture of the chips to identify defective chips that fall outside of desirable performance specifications. It is also often desirable to provide memory testing capabilities in electronic devices that incorporate such chips, e.g., using embedded built-in self-test (BIST) logic, to detect defects that may arise after manufacture and thereby ensure the continued reliability of data stored in the chips.
A number of performance characteristics are desirable for SRAM and other types of memory arrays. One such performance characteristic is stability, which generally refers to the ability of a memory cell in a memory array to maintain a given logic state after that logic state is written into the memory cell. Stability is often a critical performance metric for a memory cell, as an unstable memory cell may be susceptible to unexpectedly flipping logic states in certain circumstances, and thereby corrupting the data stored in the cell.
To provide a better understanding of the concept of stability, FIG. 1 illustrates a conventional SRAM memory cell 10 coupled between a wordline WL and pair of complementary bitlines BLC and BLT. Multiple wordlines and bitline pairs are typically provided in a memory array such that each memory cell in the array is coupled to a unique combination of wordlines and bitline pairs to permit each memory cell to be individually accessed in the array.
A conventional SRAM memory cell typically includes six metal oxide semiconductor field effect transistors (MOSFET's, or simply FET's), which are illustrated in FIG. 1 as FET's N1-N4 and P3-P4. FET's N1 and N2 are n-type MOSFET's that function as pass gates controlled by wordline WL. FET's N3 and P3 are respectively n-type and p-type FET's arranged to form an inverter, as are FET's N4 and P4. The inverters N3/P3 and N4/P4 are arranged in a cross-coupled configuration, with the output of one inverter coupled to the input of the other. Pass gate FET's N1 and N2 respectively couple the cross-coupled inverters to the BLC and BLT bitlines in response to the signal on wordline WL.
As shown in FIG. 2, data is written into an SRAM memory cell by precharging bitlines BLT, BLC to a predetermined level such as the high supply, turning off the bitline precharge devices, activating pass gates N1 and N2 by asserting wordline WL, and subsequently driving bitlines BLT and BLC to force the desired data on the bitlines. Subsequent to these operations, the internal nodes of the memory cell, illustrated at TRU and CMP (for "true" and "complementary" states) are switched to represent the appropriate state being written to the cell (e.g., a transition from a logic "1" to a logic "0" state in FIG. 2). Once the internal nodes have been switched to the proper state, pass gates N1 and N2 are shut off by deasserting wordline WL, and the bitline precharge devices are turned on to precharge the bitlines BLT and BLC to the high supply. The WRITE operation is then complete.
As shown in FIG. 3, a READ operation occurs by precharging bitlines BLT, BLC to the high supply, turning off the bitline precharge devices, activating pass gates N1 and N2 by asserting wordline WL, and then allowing the appropriate true or complement bitline BLT, BLC to be discharged depending upon the data stored in the cell (e.g., for FIG. 3, where a logic "1" state is stored in the cell, the BLC line is discharged). The state of the memory cell is then sensed by a sense amplifier coupled to the bitlines, and after sensing of the data, pass gates N1 and N2 are shut off by deasserting wordline WL, and the bitline precharge devices are again turned on to precharge the bitlines to the high supply.
Stability concerns arise in SRAM memory cells due to the relatively large capacitance of the bitlines BLT and BLC relative to the FET's in such memory cells. In particular, absent proper design and manufacture, the capacitance in the bitlines can flood from the bitlines during accesses to a memory array to switch the internal state of a memory cell, resulting in instability and unreliability of data. As shown in FIG. 3, for example, any attempt to read memory cell 10, or even any other memory cell controlled by the same wordline, results in the level at the CMP internal node rising from its zero logic state. If the CMP node rises high enough to activate the N3/P3 inverter, the cell will switch state, and thereby corrupt the data stored in the cell.
To address this difficulty, the relative sizes of pass gates N1 and N2 are typically designed relative to the pull down FET's N3 and N4 in the cross-coupled inverters to prevent charge from the bitlines from switching the internal state of the cell. However, it has been found that variations in cell widths, lengths, threshold voltages, and other manufacturing parameters can still cause instability in a memory cell, and thus memory testing is often required to ensure that manufactured components meet acceptable stability parameters.
Furthermore, certain fabrication technologies can be more susceptible to stability concerns than others. In particular, it has been found that SRAM's manufactured using silicon-on-insulator (SOI) technology may exhibit additional characteristics that impact memory stability beyond conventional bulk silicon technologies. With a conventional bulk silicon process, for example, SRAM memory cells are formed on a silicon substrate, which is typically tied to a fixed voltage level such as ground or high supply so that the bodies of the FET's are maintained at a fixed potential. With SOI technology, on the other hand, FET's are formed within an oxidized layer of insulation on a substrate that insulates the FET's from electrical effects, and permits the FET's to operate at a higher speed and with reduced power consumption. As a result, the bodies of the FET's are not tied to any fixed potential, and are thus allowed to "float" to different voltages based upon their respective switching histories.
As the body voltage of a FET changes, its characteristics, e.g., the threshold voltage required to activate the FET, also change. As such, it has been found that the switching history effect exhibited by SOI SRAM's may result in memory cells favoring one state over the other, with such favoritism typically increasing over time as a cell is maintained in the same state.
For example, FIG. 3 illustrates how the amount in which the complementary node CMP rises during a READ operation can vary depending upon switching history. In many instances, it has been found that the level in which the complementary node will rise in response to a READ operation is at a relatively low level, e.g., as represented at A in FIG. 3. However, it has also been found that, when a cell has remained in one state for a relatively long time, and thus favors that state, the cell typically has its greatest instability immediately after it is written to an opposite state, such that any READ to the memory cell or any other memory cell on the same wordline may cause the CMP node of such memory cell to rise even higher (e.g., as represented at B in FIG. 3) --potentially to a level that would switch the internal state of the memory cell.
Given that switching history does not appreciably modify the performance of memory cells formed using conventional bulk silicon processes (principally due to the fixed body potentials in the cells), conventional memory tests for bulk silicon processes do not address or accommodate for switching history effects. Accordingly, conventional memory tests are often incapable of adequately testing the potential reliability of SOI SRAM memory arrays.
Therefore, a significant need has arisen in the art for a manner of testing SOI SRAM memory cells and arrays incorporating the same so as to accommodate for switching history effects in a determination of the stability of such cells.